The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a saddle fin shaped gate that exhibits improved transistor characteristics and a corresponding method for manufacturing the same.
As the high integration of a semiconductor device proceeds to an ever higher degree of integration, the transistor channel lengths and widths decrease and the doping concentrations of junction regions at the source and drain regions increase. As a result junction leakage current increase because strong electric fields develop, a charge sharing phenomenon between the junction regions increasingly occurs, and the controllability of transistors is degraded. Accordingly, a threshold voltage abruptly decreases which is caused by short channel effects.
Therefore, it is difficult to develop a highly integrated semiconductor device that can achieve an adequate threshold voltage by using conventional planar channel structure designs for transistors. Furthermore, since gate-induced drain leakage (GIDL) increases due to the development of strong electric fields in the junction regions, then limitations necessarily arise when trying to improve on the refresh characteristics of a semiconductor device.
Under these circumstances, transistors having a three-dimensional fin channel structure have been proposed as promising candidates that may be capable of increasing the channel area while not suffering from some or all of the above noted deficiencies of high integration transistors. In fin transistor, a partial thickness of portions of an isolation structure which adjoins an active region is etched away so that the active region can protrude. As a result of this design a fin pattern is formed such that the front and rear surfaces and the upper surface of the active region are exposed. By forming a gate line that covers the fin pattern, the short channel effect can be suppressed. Because a channel is formed through the three exposed surfaces of the active region, current drivability through the channel can be significantly improved.
However, in the conventional art, as the cell size of a semiconductor device is reduced, the width of a fin pattern decreases. As a result the controllability of a gate deteriorates and drain-induced barrier lowering (DIBL) and swing properties are degraded. Whereupon the characteristics of the transistor become poor.